453 search results - page 36 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
CODES
2003
IEEE
14 years 29 days ago
2003
IEEE
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
We compare the performance of systems consisting of one large cluster containing q processors with systems where processors are grouped into k clusters containing u processors eac...