453 search results - page 64 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
CODES
2008
IEEE
14 years 3 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
APCSAC
2005
IEEE
14 years 2 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
MICRO
1991
IEEE
14 years 10 days ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
RTS
2002
13 years 8 months ago
2002
This paper presents a Feedback Control real-time Scheduling (FCS) framework for adaptive realtime systems. An advantage of the FCS framework is its use of feedback control theory ...
ADBIS
2004
Springer
14 years 2 months ago
2004
Springer
Business rules are often implemented as stored procedures in a database server. These procedures are triggered by various clients, but the execution load is fully centralized on th...