453 search results - page 69 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
CASES
2001
ACM
14 years 14 days ago
2001
ACM
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
DAC
1997
ACM
14 years 1 months ago
1997
ACM
Binary Decision Diagrams BDDs are e cient at manipulating large sets in a compact manner. BDDs, however, are inefcient at utilizing the memory hierarchy of the computer. Recent ...
DEBU
2000
13 years 8 months ago
2000
Execution plans produced by traditional query optimizers for data integration queries may yield poor performance for several reasons. The cost estimates may be inaccurate, the mem...
SPAA
2009
ACM
14 years 9 months ago
2009
ACM
Work stealing is a popular method of scheduling fine-grained parallel tasks. The performance of work stealing has been extensively studied, both theoretically and empirically, but...