453 search results - page 6 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
AGENTS
1999
Springer
13 years 12 months ago
1999
Springer
We describe the interface between a real-time resource allocation system with an AI planner in order to create fault-tolerant plans that are guaranteed to execute in hard real-tim...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
GLVLSI
2002
IEEE
14 years 16 days ago
2002
IEEE
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
EMSOFT
2004
Springer
14 years 29 days ago
2004
Springer
Cache prediction for preemptive scheduling is an open issue despite its practical importance. First analysis approaches use simplified models for cache behavior or they assume si...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...