453 search results - page 73 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
JPDC
2010
13 years 7 months ago
2010
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
ICCAD
1994
IEEE
14 years 28 days ago
1994
IEEE
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
RTSS
1996
IEEE
14 years 29 days ago
1996
IEEE
An integrated platform which is capable of meeting the requirements of both traditional real-time control processing and multimedia processing has enormous potential for accommoda...
EUROPAR
2001
Springer
14 years 1 months ago
2001
Springer
A swap instruction, which exchanges a value in memory with a value of a register, is available on many architectures. The primary application of a swap instruction has been for pro...