Sciweavers

555 search results - page 94 / 111
» Execution levels for aspect-oriented programming
Sort
View
EDBTW
2010
Springer
14 years 26 days ago
Declarative scheduling in highly scalable systems
In modern architectures based on Web Services or Cloud Computing, a very large number of user requests arrive concurrently and has to be scheduled for execution constrained by cor...
Christian Tilgner
HPCC
2009
Springer
14 years 11 days ago
On the Performance of Commit-Time-Locking Based Software Transactional Memory
Compared with lock-based synchronization techniques, Software Transactional Memory (STM) can significantly improve the programmability of multithreaded applications. Existing res...
Zhengyu He, Bo Hong
IEEEPACT
2000
IEEE
14 years 4 days ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 4 days ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
ACMSE
2000
ACM
14 years 3 days ago
Hyperscenarios: a framework for active narrative
Scenarios are narratives that illustrate future possibilities, such as proposed systems or plans, and help policy makers and designers choose among alternative courses of action. ...
Reginald L. Hobbs, Colin Potts