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» Execution levels for aspect-oriented programming
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ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
14 years 1 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
PLDI
2005
ACM
14 years 1 months ago
Register allocation for software pipelined multi-dimensional loops
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
Hongbo Rong, Alban Douillet, Guang R. Gao
ASPLOS
2004
ACM
14 years 1 months ago
An ultra low-power processor for sensor networks
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
Virantha N. Ekanayake, Clinton Kelly IV, Rajit Man...
CLADE
2003
IEEE
14 years 1 months ago
vGrid: A Framework For Building Autonomic Applications
With rapid technological advances in network infrastructure, programming languages, compatible component interfaces and so many more areas, today the computational Grid has evolve...
Bithika Khargharia, Salim Hariri, Manish Parashar,...
DAGSTUHL
2003
13 years 9 months ago
Components, Features, and Agents in the ABC
Abstract. In this paper, we show how the concepts of objects, components, features and agents are used today in the Agent Building Center (ABC) environment in order to marry the mo...
Tiziana Margaria