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» Execution-Driven Simulators for Parallel Systems Design
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SAC
2006
ACM
15 years 8 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
SI3D
1995
ACM
15 years 6 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 7 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
ACSD
2010
IEEE
255views Hardware» more  ACSD 2010»
15 years 15 days ago
From POOSL to UPPAAL: Transformation and Quantitative Analysis
POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control syst...
Jiansheng Xing, Bart D. Theelen, Rom Langerak, Jac...
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
15 years 7 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...