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» Experiences in Hardware Trojan Design and Implementation
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FCCM
2007
IEEE
115views VLSI» more  FCCM 2007»
14 years 3 months ago
Generating FPGA-Accelerated DFT Libraries
We present a domain-specific approach to generate highperformance hardware-software partitioned implementations of the discrete Fourier transform (DFT) in fixed point precision....
Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryh...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 5 months ago
Fast wire length estimation by net bundling for block placement
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
Tan Yan, Hiroshi Murata
TEI
2010
ACM
268views Hardware» more  TEI 2010»
14 years 3 months ago
DisplayObjects: prototyping functional physical interfaces on 3d styrofoam, paper or cardboard models
This paper introduces DisplayObjects, a rapid prototyping workbench that allows functional interfaces to be projected onto real 3D physical prototypes. DisplayObjects uses a Vicon...
Eric Akaoka, Tim Ginn, Roel Vertegaal
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 3 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
DATE
2003
IEEE
69views Hardware» more  DATE 2003»
14 years 2 months ago
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
Ulrich Seidl, Klaus Eckl, Frank M. Johannes