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ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 5 months ago
Distributed Reorder Buffer Schemes for Low Power
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad ...
FM
2009
Springer
154views Formal Methods» more  FM 2009»
13 years 6 months ago
Specification and Verification of Web Applications in Rewriting Logic
Abstract. This paper presents a Rewriting Logic framework that formalizes the interactions between Web servers and Web browsers through icating protocol abstracting HTTP. The propo...
María Alpuente, Demis Ballis, Daniel Romero
DAC
2005
ACM
13 years 10 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
14 years 1 months ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
HPCC
2007
Springer
14 years 2 months ago
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efï¬...
Yong Li, Zhiying Wang, Jian Ruan, Kui Dai