774 search results - page 50 / 155 » Experiences of low power design implementation and verificat... |
DAC
2007
ACM
14 years 9 months ago
2007
ACM
The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
DAC
2011
ACM
12 years 8 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
GLOBECOM
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
IPSN
2004
Springer
14 years 2 months ago
2004
Springer
The performance of a sensor network may be best judged by the quality of application specific information return. The actual sensing performance of a deployed sensor network depe...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...