774 search results - page 97 / 155 » Experiences of low power design implementation and verificat... |
GECCO
2004
Springer
14 years 2 months ago
2004
Springer
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
ARITH
2005
IEEE
14 years 2 months ago
2005
IEEE
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
IJCSS
2007
13 years 8 months ago
2007
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
EUROPAR
2010
Springer
13 years 10 months ago
2010
Springer
Mutual exclusion locks limit concurrency but offer low latency. Software transactional memory (STM) typically has higher latency, but scales well. In this paper we propose transac...