192 search results - page 11 / 39 » Experiences with the Blackfin architecture in an embedded sy... |
ECRTS
2003
IEEE
14 years 24 days ago
2003
IEEE
When time-triggered (TT) systems are to be deployed for large embedded real-time (RT) control systems in cars and airplanes, one way to overcome bandwidth limitations and achieve ...
CORR
2006
Springer
13 years 7 months ago
2006
Springer
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
CASES
2009
ACM
13 years 11 months ago
2009
ACM
2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propaga...