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» Experimental Assessment of Parallel Systems
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DAC
2005
ACM
14 years 8 months ago
Locality-conscious workload assignment for array-based computations in MPSOC architectures
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over ...
Feihui Li, Mahmut T. Kandemir
VLDB
2007
ACM
145views Database» more  VLDB 2007»
14 years 8 months ago
Executing Stream Joins on the Cell Processor
Low-latency and high-throughput processing are key requirements of data stream management systems (DSMSs). Hence, multi-core processors that provide high aggregate processing capa...
Bugra Gedik, Philip S. Yu, Rajesh Bordawekar
ICPP
2009
IEEE
14 years 2 months ago
Code Semantic-Aware Runahead Threads
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
Tanausú Ramírez, Alex Pajuelo, Olive...
HOTI
2008
IEEE
14 years 2 months ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...
CLUSTER
2007
IEEE
14 years 2 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...