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ICDCSW
2005
IEEE
14 years 1 months ago
Probability Based Power Aware Error Resilient Coding
Error resilient encoding in video communication is becoming increasingly important due to data transmission over unreliable channels. In this paper, we propose a new power-aware e...
Minyoung Kim, Hyunok Oh, Nikil D. Dutt, Alexandru ...
ICS
2009
Tsinghua U.
14 years 2 months ago
/scratch as a cache: rethinking HPC center scratch storage
To sustain emerging data-intensive scientific applications, High Performance Computing (HPC) centers invest a notable fraction of their operating budget on a specialized fast sto...
Henry M. Monti, Ali Raza Butt, Sudharshan S. Vazhk...
CCS
2007
ACM
14 years 1 months ago
SecureBus: towards application-transparent trusted computing with mandatory access control
The increasing number of software-based attacks has attracted substantial efforts to prevent applications from malicious interference. For example, Trusted Computing (TC) technolo...
Xinwen Zhang, Michael J. Covington, Songqing Chen,...
DAC
2010
ACM
13 years 11 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
TOMACS
1998
140views more  TOMACS 1998»
13 years 7 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...