Sciweavers

227 search results - page 34 / 46
» Experiments with a Parallel External Memory System
Sort
View
BCS
2008
13 years 8 months ago
A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
Andreas Fidjeland, Wayne Luk, Stephen Muggleton
GRID
2004
Springer
14 years 3 days ago
Hybrid Preemptive Scheduling of MPI Applications on the Grids
— Time sharing between all the users of a Grid is a major issue in cluster and Grid integration. Classical Grid architecture involves a higher level scheduler which submits non o...
Aurelien Bouteiller, Hinde-Lilia Bouziane, Thomas ...
TVLSI
2010
13 years 1 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
PPOPP
2010
ACM
14 years 4 months ago
NOrec: streamlining STM by abolishing ownership records
Drawing inspiration from several previous projects, we present an ownership-record-free software transactional memory (STM) system that combines extremely low overhead with unusua...
Luke Dalessandro, Michael F. Spear, Michael L. Sco...
ICS
2003
Tsinghua U.
13 years 12 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...