Sciweavers

375 search results - page 29 / 75
» Explicit gate delay model for timing evaluation
Sort
View
ASIAN
2007
Springer
157views Algorithms» more  ASIAN 2007»
16 years 1 months ago
A Logical Framework for Evaluating Network Resilience Against Faults and Attacks
Abstract. We present a logic-based framework to evaluate the resilience of computer networks in the face of incidents, i.e., attacks from malicious intruders as well as random faul...
Elie Bursztein, Jean Goubault-Larrecq
CONEXT
2006
ACM
16 years 1 months ago
Modeling the AIADD paradigm in networks with variable delays
Modeling TCP is fundamental for understanding Internet behavior. The reason is that TCP is responsible for carrying a huge quota of the Internet traffic. During last decade many a...
Gennaro Boggia, Pietro Camarda, Alessandro D'Alcon...
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
16 years 4 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
TCAD
2010
130views more  TCAD 2010»
15 years 2 months ago
On ATPG for Multiple Aggressor Crosstalk Faults
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to...
Kunal P. Ganeshpure, Sandip Kundu
INTEGRATION
2002
57views more  INTEGRATION 2002»
15 years 7 months ago
To Booth or not to Booth
Booth Recoding is a commonly used technique to recode one of the operands in binary multiplication. In this way the implementation of a multipliers' adder tree can be improve...
Wolfgang J. Paul, Peter-Michael Seidel