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» Explicit gate delay model for timing evaluation
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DAC
2006
ACM
14 years 8 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
PADS
1998
ACM
13 years 12 months ago
Optimizing Communication in Time-Warp Simulators
In message passing environments, the message send time is dominated by overheads that are relatively independent of the message size. Therefore, fine-grained applications (such a...
Malolan Chetlur, Nael B. Abu-Ghazaleh, Radharamana...
RTSS
1999
IEEE
13 years 12 months ago
Design and Evaluation of a Feedback Control EDF Scheduling Algorithm
Despite the significant body of results in real-time scheduling, many real world problems are not easily supported. While algorithms such as Earliest Deadline First, Rate Monotoni...
Chenyang Lu, John A. Stankovic, Gang Tao, Sang Hyu...
MIAR
2006
IEEE
14 years 1 months ago
Pulsative Flow Segmentation in MRA Image Series by AR Modeling and EM Algorithm
Segmentation of CSF and pulsative blood flow, based on a single phase contrast MRA (PC-MRA) image can lead to imperfect classifications. In this paper, we present a novel automated...
Ali Gooya, Hongen Liao, Kiyoshi Matsumiya, Ken Mas...
INFOCOM
2005
IEEE
14 years 1 months ago
An analytic framework for modeling peer to peer networks
Abstract—This paper presents an analytic framework to evaluate the performance of peer to peer (P2P) networks. Using the time to download or replicate an arbitrary file as the m...
Krishna K. Ramachandran, Biplab Sikdar