Standard cell characterization considering lithography induced variations

As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people often treat systematic components of the variations, which are generally traceable according to process models, in the same way as random variations in process corner based methodologies. Consequently, the process corner models are unnecessarily pessimistic. In this paper, we propose a new cell characterization methodology which captures lithography induced gate length variations. A new technique of dummy poly insertion is suggested to shield inter-cell optical interferences. This technique together with standard cells characterized using our methodology will let current design flows comprehend the variations almost without any changes. Experimental results on industrial designs indicate that our methodology can averagely reduce timing variation window by 8%-25%, power variation window by 55% when compared to a ...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Ke Cao, Sorin Dobre, Jiang Hu
• Keywords: DAC 2006, Design Automation, Gate Length Variations, Power Variation Window, Process Variations