375 search results - page 49 / 75 » Explicit gate delay model for timing evaluation |
ASPDAC
2000
ACM
14 years 1 days ago
2000
ACM
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
WSC
2007
13 years 10 months ago
2007
Event simulation and analytic modeling are used to evaluate the performance of Low Latency Queueing (LLQ), a queueing discipline available in some Internet packet switching router...
ICC
2007
IEEE
13 years 11 months ago
2007
IEEE
To increase the achievable sum rate of downlink MIMO (Multiple Input Multiple Output) systems, the cooperation among Base Stations (BS) is investigated in a slow fading channel. Th...
INFOCOM
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— We consider a multi-class queueing system operating under the Discriminatory Processor-Sharing (DPS) discipline. The DPS discipline provides a natural approach for mode...
CHI
2006
ACM
14 years 8 months ago
2006
ACM
It has been well established in Cognitive Psychology that humans are able to strategically adapt performance, even highly skilled performance, to meet explicit task goals such as ...