375 search results - page 56 / 75 » Explicit gate delay model for timing evaluation |
ISPASS
2009
IEEE
14 years 2 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
EDCC
1999
Springer
13 years 12 months ago
1999
Springer
Abstract. In this paper we present a new modelling approach for dependability evaluation and sensitivity analysis of Scheduled Maintenance Systems, based on a Deterministic and Sto...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
High assurance systems such as those found in aircraft controls and the financial industry are often required to handle a mix of tasks where some are niceties (such as the contro...
ICCAD
1993
IEEE
13 years 11 months ago
1993
IEEE
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...
CLUSTER
2009
IEEE
14 years 11 days ago
2009
IEEE
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...