375 search results - page 8 / 75 » Explicit gate delay model for timing evaluation |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
A technique based on the sensitivity of the output to input waveform is presented for accurate propagation of delay information through a gate for the purpose of static timing ana...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
DAC
2000
ACM
14 years 4 hour ago
2000
ACM
: The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...