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IJPP
2006
82views more  IJPP 2006»
13 years 7 months ago
Supporting Microthread Scheduling and Synchronisation in CMPs
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
Ian Bell, Nabil Hasasneh, Chris R. Jesshope
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
12 years 10 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
ICW
2005
IEEE
160views Communications» more  ICW 2005»
14 years 1 months ago
BAP Sparsing: A Novel Approach to MPEG-4 Body Animation Parameter Compression
The MPEG-4 standard includes support not only for natural video and audio, but also for synthetic graphics and sounds. In the MPEG-4 specifications, Body Animation Parameters (BAP...
Siddhartha Chattopadhyay, Suchendra M. Bhandarkar,...
ACMMSP
2004
ACM
125views Hardware» more  ACMMSP 2004»
14 years 26 days ago
Improving trace cache hit rates using the sliding window fill mechanism and fill select table
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
Muhammad Shaaban, Edward Mulrane