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127
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DATE
2010
IEEE
157views Hardware» more  DATE 2010»
15 years 8 months ago
RMOT: Recursion in model order for task execution time estimation in a software pipeline
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
Nabeel Iqbal, M. A. Siddique, Jörg Henkel
127
Voted
ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
15 years 8 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
134
Voted
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
15 years 8 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
SPAA
2010
ACM
15 years 8 months ago
Implementing and evaluating nested parallel transactions in software transactional memory
Transactional Memory (TM) is a promising technique that simplifies parallel programming for shared-memory applications. To date, most TM systems have been designed to efficientl...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
ICA3PP
2010
Springer
15 years 8 months ago
Modular Resultant Algorithm for Graphics Processors
Abstract. In this paper we report on the recent progress in computing bivariate polynomial resultants on Graphics Processing Units (GPU). Given two polynomials in Z[x, y], our algo...
Pavel Emeliyanenko