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Exploiting High-Level Descriptions for Circuits Fault Tolera...
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DFT
1997
IEEE
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Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments
15 years 7 months ago
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Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo...
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EVOW
2001
Springer
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Artificial Intelligence
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ARPIA: A High-Level Evolutionary Test Signal Generator
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The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
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