87 search results - page 11 / 18 » Exploiting Instruction Redundancy for Transient Fault Tolera... |
CGO
2005
IEEE
14 years 1 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
CGO
2009
IEEE
14 years 2 months ago
2009
IEEE
—As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. ...
SAFECOMP
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents an experimental evaluation of the fault-tolerant communication (FTCOM) layer of the DECOS integrated architecture. The FTCOM layer implements different agreemen...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we...
ISMVL
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...