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ET
2008
92views more  ET 2008»
13 years 7 months ago
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ET
2007
101views more  ET 2007»
13 years 7 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
GLVLSI
2010
IEEE
141views VLSI» more  GLVLSI 2010»
13 years 7 months ago
Energy-efficient redundant execution for chip multiprocessors
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chi...
Pramod Subramanyan, Virendra Singh, Kewal K. Saluj...
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
13 years 12 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
AICCSA
2006
IEEE
137views Hardware» more  AICCSA 2006»
14 years 1 months ago
Modeling Redundancy: Quantitative and Qualitative Models
Redundancy is a system property that generally refers to duplication of state information or system function. While redundancy is usually investigated in the context of fault tole...
Ali Mili, Lan Wu, Frederick T. Sheldon, Mark Shere...