1474 search results - page 213 / 295 » Exploiting Locality in a TMS |
ISCA
1999
IEEE
14 years 2 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
ISCA
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce th...
MICRO
1999
IEEE
14 years 2 months ago
1999
IEEE
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
MICRO
1998
IEEE
14 years 2 months ago
1998
IEEE
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
MICRO
1997
IEEE
14 years 2 months ago
1997
IEEE
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...