10 search results - page 1 / 2 » Exploiting Microarchitectural Redundancy For Defect Toleranc... |
ICCD
2003
IEEE
14 years 7 months ago
2003
IEEE
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...
ISCA
2005
IEEE
14 years 4 months ago
2005
IEEE
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
DAC
2005
ACM
14 years 12 months ago
2005
ACM
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
DSN
2007
IEEE
14 years 5 months ago
2007
IEEE
A new approach is proposed that exploits repetition inherent in programs to provide low-overhead transient fault protection in a processor. Programs repeatedly execute the same in...
PRDC
2006
IEEE
14 years 4 months ago
2006
IEEE
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...