87 search results - page 10 / 18 » Exploiting Postdominance for Speculative Parallelization |
CGO
2004
IEEE
14 years 1 months ago
2004
IEEE
Efficient inter-thread value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving value communication ...
PLDI
2009
ACM
14 years 4 months ago
2009
ACM
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
TCAD
2008
13 years 10 months ago
2008
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
ASPLOS
2008
ACM
14 years 2 days ago
2008
ACM
Support for optimistic parallelism such as thread-level speculation (TLS) and transactional memory (TM) has been proposed to ease the task of parallelizing software to exploit the...
IEEEPACT
1999
IEEE
14 years 2 months ago
1999
IEEE
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...