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» Exploiting Value Locality in Physical Register Files
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ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
14 years 5 months ago
Making register file resistant to power analysis attacks
— Power analysis attacks are a type of side-channel attacks that exploits the power consumption of computing devices to retrieve secret information. They are very effective in br...
Shuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhiji...
IPPS
2006
IEEE
14 years 2 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
MICRO
1996
IEEE
96views Hardware» more  MICRO 1996»
14 years 28 days ago
Exceeding the Dataflow Limit via Value Prediction
For decades, the serialization constraints imposed by true data dependences have been regarded as an absolute limit--the dataflow limit--on the parallel execution of serial progra...
Mikko H. Lipasti, John Paul Shen
FAST
2010
13 years 11 months ago
Panache: A Parallel File System Cache for Global File Access
Cloud computing promises large-scale and seamless access to vast quantities of data across the globe. Applications will demand the reliability, consistency, and performance of a t...
Marc Eshel, Roger L. Haskin, Dean Hildebrand, Mano...
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 8 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....