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» Exploiting Vector Parallelism in Software Pipelined Loops
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JSA
2000
175views more  JSA 2000»
13 years 7 months ago
Complete worst-case execution time analysis of straight-line hard real-time programs
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. The analysis is focused on straight-line code...
Friedhelm Stappert, Peter Altenbernd
EUROPAR
2009
Springer
14 years 2 months ago
Impact of Quad-Core Cray XT4 System and Software Stack on Scientific Computation
An upgrade from dual-core to quad-core AMD processor on the Cray XT system at the Oak Ridge National Laboratory (ORNL) Leadership Computing Facility (LCF) has resulted in significa...
Sadaf R. Alam, Richard F. Barrett, Heike Jagode, J...
CASES
2009
ACM
14 years 2 months ago
Fine-grain performance scaling of soft vector processors
Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
CODES
2009
IEEE
13 years 8 months ago
A scalable parallel H.264 decoder on the cell broadband engine architecture
The H.264 video codec provides exceptional video compression while imposing dramatic increases in computational complexity over previous standards. While exploiting parallelism in...
Michael A. Baker, Pravin Dalale, Karam S. Chatha, ...
CASES
2007
ACM
13 years 11 months ago
Hierarchical coarse-grained stream compilation for software defined radio
Software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application speci...
Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevo...