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ICCAD
2004
IEEE
138views Hardware» more  ICCAD 2004»
14 years 3 months ago
A thermal-driven floorplanning algorithm for 3D ICs
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
Jason Cong, Jie Wei, Yan Zhang
PPOPP
1993
ACM
13 years 10 months ago
LogP: Towards a Realistic Model of Parallel Computation
A vast body of theoretical research has focused either on overly simplistic models of parallel computation, notably the PRAM, or overly specific models that have few representati...
David E. Culler, Richard M. Karp, David A. Patters...
ICS
2007
Tsinghua U.
14 years 25 days ago
Adaptive Strassen's matrix multiplication
Strassen’s matrix multiplication (MM) has benefits with respect to any (highly tuned) implementations of MM because Strassen’s reduces the total number of operations. Strasse...
Paolo D'Alberto, Alexandru Nicolau
ICS
2000
Tsinghua U.
13 years 10 months ago
Hardware-only stream prefetching and dynamic access ordering
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
Chengqiang Zhang, Sally A. McKee
ISCAS
2003
IEEE
167views Hardware» more  ISCAS 2003»
13 years 12 months ago
The multi-level paradigm for distributed fault detection in networks with unreliable processors
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
Krishnaiyan Thulasiraman, Ming-Shan Su, V. Goel