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» Exploiting loop-dependent stream reuse for stream processors
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MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
13 years 11 months ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
SIGARCH
2008
144views more  SIGARCH 2008»
13 years 7 months ago
A stream chip-multiprocessor for bioinformatics
- Bioinformatics applications such as gene and protein sequence matching algorithms are characterized by the need to process large amounts of data. While uni-processor performance ...
Ravi Kiran Karanam, Arun Ravindran, Arindam Mukher...
SIGARCH
2008
107views more  SIGARCH 2008»
13 years 7 months ago
A lightweight streaming layer for multicore execution
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
David Zhang, Qiuyuan J. Li, Rodric Rabbah, Saman A...
DATE
2004
IEEE
146views Hardware» more  DATE 2004»
13 years 11 months ago
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
In multimedia and other streaming applications a significant portion of energy is spent on data transfers. Exploiting data reuse opportunities in the application, we can reduce th...
Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nik...
EGH
2004
Springer
13 years 11 months ago
Understanding the efficiency of GPU algorithms for matrix-matrix multiplication
Utilizing graphics hardware for general purpose numerical computations has become a topic of considerable interest. The implementation of streaming algorithms, typified by highly ...
Kayvon Fatahalian, Jeremy Sugerman, Pat Hanrahan