283 search results - page 40 / 57 » Exploiting parallel networks using dynamic channel schedulin... |
HPCA
1998
IEEE
14 years 26 days ago
1998
IEEE
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
ICDCS
2005
IEEE
14 years 2 months ago
2005
IEEE
DualPats exploits the strong correlation between TCP throughput and flow size, and the statistical stability of Internet path characteristics to accurately predict the TCP throug...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
ISVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...
DSD
2002
IEEE
14 years 1 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...