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» Exploiting regularity for low-power design
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ICIP
2003
IEEE
14 years 11 months ago
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores
For motion estimation (ME) and discrete cosine transform (DCT) of MPEG video encoding, content variation and perceptual tolerance in video signals can be exploited to gracefully t...
Andrew Laffely, Jian Liang, Russell Tessier, Wayne...
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 4 months ago
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim...
HPCA
2005
IEEE
14 years 3 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
TACAS
2007
Springer
117views Algorithms» more  TACAS 2007»
14 years 3 months ago
Replaying Play In and Play Out: Synthesis of Design Models from Scenarios by Learning
This paper is concerned with bridging the gap between requirements, provided as a set of scenarios, and conforming design models. The novel aspect of our approach is to exploit lea...
Benedikt Bollig, Joost-Pieter Katoen, Carsten Kern...
GECCO
2007
Springer
182views Optimization» more  GECCO 2007»
14 years 4 months ago
Generating large-scale neural networks through discovering geometric regularities
Connectivity patterns in biological brains exhibit many repeating motifs. This repetition mirrors inherent geometric regularities in the physical world. For example, stimuli that ...
Jason Gauci, Kenneth O. Stanley