Sciweavers

148 search results - page 5 / 30
» Exploiting regularity for low-power design
Sort
View
ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
14 years 4 months ago
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
Krishnan Srinivasan, Karam S. Chatha, Goran Konjev...
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
14 years 4 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
RTSS
2009
IEEE
14 years 2 months ago
Multi-Channel Interference Measurement and Modeling in Low-Power Wireless Networks
Abstract—Multi-channel design has received significant attention for low-power wireless networks (LWNs), such as 802.15.4-based wireless sensor networks, due to its potential of...
Guoliang Xing, Mo Sha, Jun Huang, Gang Zhou, Xiaor...
JSA
2000
96views more  JSA 2000»
13 years 7 months ago
Design techniques for low-power systems
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power d...
Paul J. M. Havinga, Gerard J. M. Smit
DSD
2008
IEEE
187views Hardware» more  DSD 2008»
14 years 1 months ago
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...