33 search results - page 3 / 7 » Exploring Performance Tradeoffs for Clustered VLIW ASIPs |
SAC
2004
ACM
14 years 1 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
CASES
2001
ACM
14 years 4 days ago
2001
ACM
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...