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» Exploring the Limits of Sub-Word Level Parallelism
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MSO
2003
13 years 8 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
ISORC
2002
IEEE
14 years 13 days ago
Using Group Communication to Support Mobile Augmented Reality Applications
Augmented reality and group communication in wireless ad-hoc networks form relatively new fields of research. When using group communication ordering and timeliness requirements ...
Niels Reijers, Raymond Cunningham, René Mei...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 5 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
IEEEPACT
2009
IEEE
14 years 2 months ago
Quantifying the Potential of Program Analysis Peripherals
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...
Mohit Tiwari, Shashidhar Mysore, Timothy Sherwood
ICCD
2004
IEEE
125views Hardware» more  ICCD 2004»
14 years 4 months ago
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
Sriram Nadathur, Akhilesh Tyagi