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» Exploring the multiple-GPU design space
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RTCSA
2007
IEEE
14 years 4 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
HRI
2006
ACM
14 years 4 months ago
Service robots in the domestic environment: a study of the roomba vacuum in the home
Domestic service robots have long been a staple of science fiction and commercial visions of the future. Until recently, we have only been able to speculate about what the experie...
Jodi Forlizzi, Carl F. DiSalvo
ASPDAC
2004
ACM
83views Hardware» more  ASPDAC 2004»
14 years 3 months ago
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline
Much attention has been directed to different aspects of the design of pipelines [1,2,3,4]. Design of the control logic of non-linear pipelines has however, been considered as a su...
Hashem Hashemi Najaf-abadi
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
14 years 3 months ago
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as...
Abhik Roychoudhury, Tulika Mitra, S. R. Karri
IPPS
2003
IEEE
14 years 3 months ago
System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC
To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several meth...
Antti Pelkonen, Kostas Masselos, Miroslav Cup&aacu...