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» Exploring the multiple-GPU design space
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VIS
2007
IEEE
181views Visualization» more  VIS 2007»
14 years 11 months ago
Shadow-Driven 4D Haptic Visualization
Just as we can work with two-dimensional floor plans to communicate 3D architectural design, we can exploit reduced-dimension shadows to manipulate the higher-dimensional objects ...
Hui Zhang, Andrew J. Hanson
CEC
2010
IEEE
13 years 11 months ago
Constrained global optimization of low-thrust interplanetary trajectories
The optimization of spacecraft trajectories can be formulated as a global optimization task. The complexity of the problem depends greatly on the problem formulation, on the spacec...
Chit Hong Yam, David Di Lorenzo, Dario Izzo
IVS
2008
121views more  IVS 2008»
13 years 10 months ago
Using treemaps for variable selection in spatio-temporal visualisation
We demonstrate and reflect upon the use of enhanced treemaps that incorporate spatial and temporal ordering for exploring a large multivariate spatio-temporal data set. The result...
Aidan Slingsby, Jason Dykes, Jo Wood
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 4 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
CASES
2006
ACM
14 years 4 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...