Sciweavers

621 search results - page 14 / 125
» Extending Platform-Based Design to Network on Chip Systems
Sort
View
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
14 years 1 months ago
A methodology for mapping multiple use-cases onto networks on chips
A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for future Systems on C...
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
SDL
2003
147views Hardware» more  SDL 2003»
13 years 9 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
FPL
2009
Springer
105views Hardware» more  FPL 2009»
13 years 11 months ago
Run-time resource management in fault-tolerant network on reconfigurable chips
This paper investigates the challenges of run-time resource management in future coarse-grained network-onreconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature e...
Mohammad Hosseinabady, José L. Nú&nt...
DSD
2010
IEEE
221views Hardware» more  DSD 2010»
13 years 5 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...
IJCNN
2000
IEEE
14 years 5 days ago
Simulation of a Digital Neuro-Chip for Spiking Neural Networks
: Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with ...
Tim Schönauer, S. Atasoy, N. Mehrtash, Heinri...