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CODES
2006
IEEE
13 years 11 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
HPCC
2005
Springer
14 years 2 months ago
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
Francisco J. Villa, Manuel E. Acacio, José ...
MOBICOM
2012
ACM
11 years 11 months ago
CloudIQ: a framework for processing base stations in a data center
The cellular industry is evaluating architectures to distribute the signal processing in radio access networks. One of the options is to process the signals of all base stations o...
Sourjya Bhaumik, Shoban Preeth Chandrabose, Manjun...
SIGCOMM
2009
ACM
14 years 3 months ago
SmartRE: an architecture for coordinated network-wide redundancy elimination
Application-independent Redundancy Elimination (RE), or identifying and removing repeated content from network transfers, has been used with great success for improving network pe...
Ashok Anand, Vyas Sekar, Aditya Akella
AI
1998
Springer
14 years 1 months ago
A Heuristic Incremental Modeling Approach to Course Timetabling
Abstract. The general timetabling problem is an assignment of activities to xed time intervals, adhering to a prede ned set of resource availabilities. Timetabling problems are di ...
Don Banks, Peter van Beek, Amnon Meisels