59 search results - page 6 / 12 » Extending the transaction level modeling approach for fast c... |
SP
1997
IEEE
13 years 11 months ago
1997
IEEE
The computer industry is increasingly dependent on open architectural standards for their competitive success. This paper describes a new approach to secure system design in which...
CODES
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...