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DATE
2010
IEEE
162views Hardware» more  DATE 2010»
14 years 5 hour ago
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Ricca...
VTS
2007
IEEE
100views Hardware» more  VTS 2007»
14 years 1 months ago
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology
In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the “Primary Input (P...
Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srik...
DKE
2010
112views more  DKE 2010»
13 years 7 months ago
An integer programming based approach for verification and diagnosis of workflows
Workflow analysis is indispensable to capture modeling errors in workflow designs. While several workflow analysis approaches have been defined previously, these approaches do not...
Rik Eshuis, Akhil Kumar
ICCD
2004
IEEE
91views Hardware» more  ICCD 2004»
14 years 3 months ago
Diagnosis of Hold Time Defects
In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. In...
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han T...
DAC
2009
ACM
14 years 8 months ago
Debugging strategies for mere mortals
Recent improvements in design verification strive to automate error detection and greatly enhance engineers' ability to detect functional errors. However, the process of diag...
Valeria Bertacco