276 search results - page 16 / 56 » Extremely Low-Power Logic |
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
CHI
2005
ACM
14 years 8 months ago
2005
ACM
Recent years have seen the evolution of networks of tiny low power computing blocks, known as sensor networks. In one class of sensor networks, a non-expert user, who has little o...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
ISLPED
2009
ACM
14 years 8 days ago
2009
ACM
We present experimental analysis to exploit the sequence dependence on energy saving in error tolerant image processing. Our analysis shows that the error distributions depend not...