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ASIACRYPT
2001
Springer
14 years 3 days ago
A Compact Rijndael Hardware Architecture with S-Box Optimization
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all...
Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji M...
ARITH
2007
IEEE
13 years 11 months ago
Robust Energy-Efficient Adder Topologies
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...
Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, R...
ICSE
2000
IEEE-ACM
13 years 11 months ago
Mathematical foundations of software engineering: a roadmap
Although we do not profess to be capable of defining a `roadmap' for the foundations of SE over the next ten years, we can discern some important steps that would be extremel...
T. S. E. Maibaum
FPGA
2008
ACM
191views FPGA» more  FPGA 2008»
13 years 9 months ago
A hardware framework for the fast generation of multiple long-period random number streams
Stochastic simulations and other scientific applications that depend on random numbers are increasingly implemented in a parallelized manner in programmable logic. High-quality ps...
Ishaan L. Dalal, Deian Stefan
CLA
2004
13 years 9 months ago
A Semi-automatic Method to Ontology Design by Using FCA
Ontology design is a complex and time-consuming process. It is extremely difficult for human experts to discover ontology from given data or texts. This paper presents a semi-autom...
Hele-Mai Haav