A Compact Rijndael Hardware Architecture with S-Box Optimization

Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all arithmetic components are reused. By introducing a new composite field, the S-Box structure is also optimized. An extremely small size of 5.4 Kgates is obtained for a 128-bit key Rijndael circuit using a 0.11-µm CMOS standard cell library. It requires only 0.052 mm2 of area to support both encryption and decryption with 311 Mbps throughput. By making effective use of the SPN parallel feature, the throughput can be boosted up to 2.6

• Type: Conference
• Year: 2001
• Where: ASIACRYPT
• Authors: Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh
• Keywords: 128-bit Key Rijndael, Aes Algorithm Rijndael, ASIACRYPT 2001, Cryptology, Decryption Data Paths