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» Extremely Low-Power Logic
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IPPS
2005
IEEE
14 years 1 months ago
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing
“MegaProto” is a proof-of-concept prototype for our project “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, implementing our key idea that a mi...
Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sat...
DAC
2005
ACM
14 years 8 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
CODES
2004
IEEE
13 years 11 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
ISLPED
2003
ACM
149views Hardware» more  ISLPED 2003»
14 years 24 days ago
Elements of low power design for integrated systems
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
Sung-Mo Kang
GLVLSI
1999
IEEE
91views VLSI» more  GLVLSI 1999»
13 years 12 months ago
A Novel Low Power Energy Recovery Full Adder Cell
A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder...
R. Shalem, Lizy Kurian John, Eugene John