Sciweavers

8 search results - page 2 / 2
» FBT: filled buffer technique to reduce code size for VLIW pr...
Sort
View
EUROPAR
2010
Springer
13 years 7 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
KBSE
2005
IEEE
14 years 1 months ago
Locating faulty code using failure-inducing chops
Software debugging is the process of locating and correcting faulty code. Prior techniques to locate faulty code either use program analysis techniques such as backward dynamic pr...
Neelam Gupta, Haifeng He, Xiangyu Zhang, Rajiv Gup...
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...